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Reducing the Soft-Error Rate of a High-Performance Microprocessor
November/December 2004 (vol. 24 no. 6)
pp. 30-37
Joel Emer, Intel
Steven K. Reinhardt, University of Michigan
Unlike traditional approaches, which focus on detecting and recovering from faults, the techniques introduced here reduce the probability that a fault will cause a declared error. the first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation.
Citation:
Christopher T. Weaver, Joel Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt, "Reducing the Soft-Error Rate of a High-Performance Microprocessor," IEEE Micro, vol. 24, no. 6, pp. 30-37, Nov.-Dec. 2004, doi:10.1109/MM.2004.86
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