Issue No.06 - November/December (2004 vol.24)
Christopher T. Weaver , Intel
Joel Emer , Intel
Shubhendu S. Mukherjee , Intel
Steven K. Reinhardt , University of Michigan
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.86
Unlike traditional approaches, which focus on detecting and recovering from faults, the techniques introduced here reduce the probability that a fault will cause a declared error. the first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation.
Christopher T. Weaver, Joel Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt, "Reducing the Soft-Error Rate of a High-Performance Microprocessor", IEEE Micro, vol.24, no. 6, pp. 30-37, November/December 2004, doi:10.1109/MM.2004.86