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Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation
November/December 2004 (vol. 24 no. 6)
pp. 10-20
| ASCII Text | x | ||
| Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Kriszti? Flautner, "Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation," IEEE Micro, vol. 24, no. 6, pp. 10-20, November/December, 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2004.85, author = {Dan Ernst and Shidhartha Das and Seokwoo Lee and David Blaauw and Todd Austin and Trevor Mudge and Nam Sung Kim and Kriszti? Flautner}, title = {Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation}, journal ={IEEE Micro}, volume = {24}, number = {6}, issn = {0272-1732}, year = {2004}, pages = {10-20}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.85}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation IS - 6 SN - 0272-1732 SP10 EP20 EPD - 10-20 A1 - Dan Ernst, A1 - Shidhartha Das, A1 - Seokwoo Lee, A1 - David Blaauw, A1 - Todd Austin, A1 - Trevor Mudge, A1 - Nam Sung Kim, A1 - Kriszti? Flautner, PY - 2004 VL - 24 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.85
Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. Here is a dvs approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.
Citation:
Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Kriszti? Flautner, "Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation," IEEE Micro, vol. 24, no. 6, pp. 10-20, Nov.-Dec. 2004, doi:10.1109/MM.2004.85
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