Issue No.04 - July/August (2004 vol.24)
Sridhar Rajagopal , WiQuest Communications
Joseph R. Cavallaro , Rice University
Scott Rixner , Rice University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.25
This tool explores tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units' organization and utilization. The exploration methodology is applicable to all embedded-processor designs in signal and media processing.
Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner, "Design Space Exploration for Real-Time Embedded Stream Processors", IEEE Micro, vol.24, no. 4, pp. 54-66, July/August 2004, doi:10.1109/MM.2004.25