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Issue No.04 - July/August (2004 vol.24)
pp: 33-41
Hsien-Hsin S. Lee , Georgia Institute of Technology
Taeweon Suh , Georgia Institute of Technology
ABSTRACT
This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.
CITATION
Hsien-Hsin S. Lee, Taeweon Suh, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1", IEEE Micro, vol.24, no. 4, pp. 33-41, July/August 2004, doi:10.1109/MM.2004.33
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