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Issue No.02 - March/April (2004 vol.24)
pp: 10-18
Stefan Rusu , Intel Corp.
Harry Muljono , Intel Corp.
Brian Cherkauer , Intel Corp.
ABSTRACT
In designing the next generation of the Itanium 2 processor, Intel doubled the on-die, level-three cache to 6 Mbytes and increased frequency by 50 percent compared to the previous generation. Another goal was to keep the power dissipation of the new design within the same envelope as its predecessor.
CITATION
Stefan Rusu, Harry Muljono, Brian Cherkauer, "Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache", IEEE Micro, vol.24, no. 2, pp. 10-18, March/April 2004, doi:10.1109/MM.2004.1289279
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