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Measuring Architectural Vulnerability Factors
November/December 2003 (vol. 23 no. 6)
pp. 70-75
Christopher T. Weaver, Intel, University of Michigan
Joel Emer, Intel
Steven K. Reinhardt, Intel, University of Michigan
Todd Austin, University of Michigan

Processor designers need accurate estimates of soft-error rates early in the design cycle to make appropriate cost-reliability tradeoffs. Here, the authors present a method for estimating the architectural vulnerability factor—the probability that a fault in a particular structure will result in an error.

Citation:
Shubhendu S. Mukherjee, Christopher T. Weaver, Joel Emer, Steven K. Reinhardt, Todd Austin, "Measuring Architectural Vulnerability Factors," IEEE Micro, vol. 23, no. 6, pp. 70-75, Nov.-Dec. 2003, doi:10.1109/MM.2003.1261389
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