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Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers
November/December 2003 (vol. 23 no. 6)
pp. 11-19
| ASCII Text | x | ||
| Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, "Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers," IEEE Micro, vol. 23, no. 6, pp. 11-19, November/December, 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2003.1261382, author = {Haitham Akkary and Ravi Rajwar and Srikanth T. Srinivasan}, title = {Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers}, journal ={IEEE Micro}, volume = {23}, number = {6}, issn = {0272-1732}, year = {2003}, pages = {11-19}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261382}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers IS - 6 SN - 0272-1732 SP11 EP19 EPD - 11-19 A1 - Haitham Akkary, A1 - Ravi Rajwar, A1 - Srikanth T. Srinivasan, PY - 2003 VL - 23 JA - IEEE Micro ER - | |||
Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structures, and provides a promising microarchitecture for future high-performance processors.
Citation:
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, "Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers," IEEE Micro, vol. 23, no. 6, pp. 11-19, Nov.-Dec. 2003, doi:10.1109/MM.2003.1261382
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