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Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers
November/December 2003 (vol. 23 no. 6)
pp. 11-19
Haitham Akkary, Portland State University
Ravi Rajwar, Intel Microarchitecture Research Lab
Srikanth T. Srinivasan, Intel Microarchitecture Research Lab

Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structures, and provides a promising microarchitecture for future high-performance processors.

Citation:
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, "Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers," IEEE Micro, vol. 23, no. 6, pp. 11-19, Nov.-Dec. 2003, doi:10.1109/MM.2003.1261382
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