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The iCore 520-MHz Synthesizable CPU Core
May/June 2003 (vol. 23 no. 3)
pp. 46-57
Nick Richardson, STMicroelectronics
Lun Bin Huang, STMicroelectronics
Razak Hossain, STMicroelectronics
Julian Lewis, STMicroelectronics
Tommy Zounes, STMicroelectronics
Naresh Soni, STMicroelectronics

A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.

Citation:
Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni, "The iCore 520-MHz Synthesizable CPU Core," IEEE Micro, vol. 23, no. 3, pp. 46-57, May-June 2003, doi:10.1109/MM.2003.1209466
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