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Efficient Construction of Aliasing-Free Compaction Circuitry
September/October 2002 (vol. 22 no. 5)
pp. 82-92

Parallel testing of cores can reduce soc test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize parallelism by minimizing the required test bandwidth at the core outputs.

Citation:
Ozgur Sinanoglu, Alex Orailoglu, "Efficient Construction of Aliasing-Free Compaction Circuitry," IEEE Micro, vol. 22, no. 5, pp. 82-92, Sept.-Oct. 2002, doi:10.1109/MM.2002.1044302
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