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Issue No.05 - September/October (2002 vol.22)
pp: 69-81
ABSTRACT
<p>Integrating reusable cores from multiple sources is essential in system-on-a-chip design. The authors present a hierarchical methodology for testing these cores and the integrated system chip.</p>
CITATION
Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Jin-Fu Li, "A Hierarchical Test Methodology for Systems on Chip", IEEE Micro, vol.22, no. 5, pp. 69-81, September/October 2002, doi:10.1109/MM.2002.1044301
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