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A Scalable High-Performance Computing Solution for Networks on Chips
September/October 2002 (vol. 22 no. 5)
pp. 46-55

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.

Citation:
Martti Forsell, "A Scalable High-Performance Computing Solution for Networks on Chips," IEEE Micro, vol. 22, no. 5, pp. 46-55, Sept.-Oct. 2002, doi:10.1109/MM.2002.1044299
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