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Issue No.05 - September/October (2002 vol.22)
pp: 46-55
ABSTRACT
<p>The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.</p>
CITATION
Martti Forsell, "A Scalable High-Performance Computing Solution for Networks on Chips", IEEE Micro, vol.22, no. 5, pp. 46-55, September/October 2002, doi:10.1109/MM.2002.1044299
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