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A Scalable High-Performance Computing Solution for Networks on Chips
September/October 2002 (vol. 22 no. 5)
pp. 46-55
| ASCII Text | x | ||
| Martti Forsell, "A Scalable High-Performance Computing Solution for Networks on Chips," IEEE Micro, vol. 22, no. 5, pp. 46-55, September/October, 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2002.1044299, author = {Martti Forsell}, title = {A Scalable High-Performance Computing Solution for Networks on Chips}, journal ={IEEE Micro}, volume = {22}, number = {5}, issn = {0272-1732}, year = {2002}, pages = {46-55}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044299}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - A Scalable High-Performance Computing Solution for Networks on Chips IS - 5 SN - 0272-1732 SP46 EP55 EPD - 46-55 A1 - Martti Forsell, PY - 2002 VL - 22 JA - IEEE Micro ER - | |||
The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.
Citation:
Martti Forsell, "A Scalable High-Performance Computing Solution for Networks on Chips," IEEE Micro, vol. 22, no. 5, pp. 46-55, Sept.-Oct. 2002, doi:10.1109/MM.2002.1044299
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