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Issue No.05 - September/October (2002 vol.22)
pp: 24-35
ABSTRACT
<p>Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.</p>
CITATION
Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design", IEEE Micro, vol.22, no. 5, pp. 24-35, September/October 2002, doi:10.1109/MM.2002.1044297
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