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Coping with Latency in SOC Design
September/October 2002 (vol. 22 no. 5)
pp. 24-35
| ASCII Text | x | ||
| Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design," IEEE Micro, vol. 22, no. 5, pp. 24-35, September/October, 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2002.1044297, author = {Luca P. Carloni and Alberto L. Sangiovanni-Vincentelli}, title = {Coping with Latency in SOC Design}, journal ={IEEE Micro}, volume = {22}, number = {5}, issn = {0272-1732}, year = {2002}, pages = {24-35}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044297}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Coping with Latency in SOC Design IS - 5 SN - 0272-1732 SP24 EP35 EPD - 24-35 A1 - Luca P. Carloni, A1 - Alberto L. Sangiovanni-Vincentelli, PY - 2002 VL - 22 JA - IEEE Micro ER - | |||
Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.
Citation:
Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, "Coping with Latency in SOC Design," IEEE Micro, vol. 22, no. 5, pp. 24-35, Sept.-Oct. 2002, doi:10.1109/MM.2002.1044297
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