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Chain: A Delay-Insensitive Chip Area Interconnect
September/October 2002 (vol. 22 no. 5)
pp. 16-23

The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. the authors propose a mixed system as a solution.

Citation:
John Bainbridge, Steve Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, no. 5, pp. 16-23, Sept.-Oct. 2002, doi:10.1109/MM.2002.1044296
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