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Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture
May/June 2002 (vol. 22 no. 3)
pp. 52-61
| ASCII Text | x | ||
| Marek Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Jozwiak, "Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture," IEEE Micro, vol. 22, no. 3, pp. 52-61, May/June, 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2002.1013304, author = {Marek Perkowski and David Foote and Qihong Chen and Anas Al-Rabadi and Lech Jozwiak}, title = {Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture}, journal ={IEEE Micro}, volume = {22}, number = {3}, issn = {0272-1732}, year = {2002}, pages = {52-61}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1013304}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture IS - 3 SN - 0272-1732 SP52 EP61 EPD - 52-61 A1 - Marek Perkowski, A1 - David Foote, A1 - Qihong Chen, A1 - Anas Al-Rabadi, A1 - Lech Jozwiak, PY - 2002 VL - 22 JA - IEEE Micro ER - | |||
A massively parallel reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation.
Citation:
Marek Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Jozwiak, "Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture," IEEE Micro, vol. 22, no. 3, pp. 52-61, May-June 2002, doi:10.1109/MM.2002.1013304
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