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Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture
May/June 2002 (vol. 22 no. 3)
pp. 52-61

A massively parallel reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation.

Citation:
Marek Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Jozwiak, "Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture," IEEE Micro, vol. 22, no. 3, pp. 52-61, May-June 2002, doi:10.1109/MM.2002.1013304
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