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Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach
May/June 2002 (vol. 22 no. 3)
pp. 41-51

The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation.

Citation:
Marek Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Jozwiak, "Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach," IEEE Micro, vol. 22, no. 3, pp. 41-51, May-June 2002, doi:10.1109/MM.2002.1013303
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