This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Cached DRAM for ILP Processor Memory Access Latency Reduction
July/August 2001 (vol. 21 no. 4)
pp. 22-32
ASCII Text
x 
 
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang, "Cached DRAM for ILP Processor Memory Access Latency Reduction," IEEE Micro, vol. 21, no. 4, pp. 22-32, July/August, 2001.
 
 
BibTex
x
 
@article{ 10.1109/40.946676,
author = {Zhao Zhang and Zhichun Zhu and Xiaodong Zhang},
title = {Cached DRAM for ILP Processor Memory Access Latency Reduction},
journal ={IEEE Micro},
volume = {21},
number = {4},
issn = {0272-1732},
year = {2001},
pages = {22-32},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.946676},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Cached DRAM for ILP Processor Memory Access Latency Reduction
IS - 4
SN - 0272-1732
SP22
EP32
EPD - 22-32
A1 - Zhao Zhang,
A1 - Zhichun Zhu,
A1 - Xiaodong Zhang,
PY - 2001
VL - 21
JA - IEEE Micro
ER -
 
Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced dram techniques for reducing memory access latency in instruction-level-parallelism processors.
Citation:
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang, "Cached DRAM for ILP Processor Memory Access Latency Reduction," IEEE Micro, vol. 21, no. 4, pp. 22-32, July-Aug. 2001, doi:10.1109/40.946676
Usage of this product signifies your acceptance of the Terms of Use.