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Cached DRAM for ILP Processor Memory Access Latency Reduction
July/August 2001 (vol. 21 no. 4)
pp. 22-32
Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced dram techniques for reducing memory access latency in instruction-level-parallelism processors.
Citation:
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang, "Cached DRAM for ILP Processor Memory Access Latency Reduction," IEEE Micro, vol. 21, no. 4, pp. 22-32, July-Aug. 2001, doi:10.1109/40.946676
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