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A Delay Model for Router Microarchitectures
January/February 2001 (vol. 21 no. 1)
pp. 26-34
ASCII Text
x 
 
Li-Shiuan Peh, William J. Dally, "A Delay Model for Router Microarchitectures," IEEE Micro, vol. 21, no. 1, pp. 26-34, January/February, 2001.
 
 
BibTex
x
 
@article{ 10.1109/40.903059,
author = {Li-Shiuan Peh and William J. Dally},
title = {A Delay Model for Router Microarchitectures},
journal ={IEEE Micro},
volume = {21},
number = {1},
issn = {0272-1732},
year = {2001},
pages = {26-34},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.903059},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - A Delay Model for Router Microarchitectures
IS - 1
SN - 0272-1732
SP26
EP34
EPD - 26-34
A1 - Li-Shiuan Peh,
A1 - William J. Dally,
PY - 2001
VL - 21
JA - IEEE Micro
ER -
 
Given router parameters, this delay model prescribes realistic pipelines, enabling router architects to optimize network performance before beginning actual detailed design.
Citation:
Li-Shiuan Peh, William J. Dally, "A Delay Model for Router Microarchitectures," IEEE Micro, vol. 21, no. 1, pp. 26-34, Jan.-Feb. 2001, doi:10.1109/40.903059
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