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A Delay Model for Router Microarchitectures
January/February 2001 (vol. 21 no. 1)
pp. 26-34
Given router parameters, this delay model prescribes realistic pipelines, enabling router architects to optimize network performance before beginning actual detailed design.
Citation:
Li-Shiuan Peh, William J. Dally, "A Delay Model for Router Microarchitectures," IEEE Micro, vol. 21, no. 1, pp. 26-34, Jan.-Feb. 2001, doi:10.1109/40.903059
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