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The MAJC Architecture: A Synthesis of Parallelism and Scalability
November/December 2000 (vol. 20 no. 6)
pp. 12-25
The MAJC(tm) microprocessor architecture was developed by Sun Microsystems to address the extreme computation requirements needed by the emerging world of broadband services. Application performance is reached by exploiting parallelism at multiple levels. First and foremost, the architecture is inherently multithreaded. The ISA supports vertical multithreading, speculative multithreading and chip multiprocessors. Secondly, the MAJC VLIW architecture is capable of advanced speculation and predication. Finally, the architecture is heavily SIMD and treats all data types similarly (unified register file, unified execution resources, etc.).
Citation:
Marc Tremblay, Jeffrey Chan, Shailender Chaudhry, Andrew W. Conigliaro, Shing Sheung Tse, "The MAJC Architecture: A Synthesis of Parallelism and Scalability," IEEE Micro, vol. 20, no. 6, pp. 12-25, Nov.-Dec. 2000, doi:10.1109/40.888700
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