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Issue No.05 - September/October (2000 vol.20)
pp: 24-43
ABSTRACT
This article describes the microarchitecture of the Itanium(tm) processor, which is the first implementation of the IA-64 instruction set architecture. The processor is optimized to meet a wide range of requirements - high performance on Internet servers and workstations, support for 64bits of addressing, reliability for mission-critical applications, full IA-32 instruction set compatibility in hardware, and scalability across a range of operating systems and platforms
CITATION
Harsh Sharangpani, Ken Arora, "Itanium Processor Microarchitecture", IEEE Micro, vol.20, no. 5, pp. 24-43, September/October 2000, doi:10.1109/40.877948
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