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The Stanford Hydra CMP
March/April 2000 (vol. 20 no. 2)
pp. 71-84
Chip multiprocessors offer an economical, scalable architecture for future microprocessors. Thread-level speculation support allows them to speed up past software.
Citation:
Lance Hammond, Benedict A. Hubbert, Michael Siu, Manohar K. Prabhu, Michael Chen, Kunle Olukotun, "The Stanford Hydra CMP," IEEE Micro, vol. 20, no. 2, pp. 71-84, March-April 2000, doi:10.1109/40.848474
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