Issue No.01 - January/February (2000 vol.20)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.820055
This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 Mflops (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point).
Jose Fridman, Zvi Greenfield, "The TigerSHARC DSP Architecture", IEEE Micro, vol.20, no. 1, pp. 66-76, January/February 2000, doi:10.1109/40.820055