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A Scheduler ASIC for a Programmable Packet Switch
January/February 2000 (vol. 20 no. 1)
pp. 42-48
| ASCII Text | x | ||
| L. Louis Zhang, Brent Beacham, Massoud Reza Hashemi, Paul Chow, Alberto Leon-Garcia, "A Scheduler ASIC for a Programmable Packet Switch," IEEE Micro, vol. 20, no. 1, pp. 42-48, January/February, 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/40.820052, author = {L. Louis Zhang and Brent Beacham and Massoud Reza Hashemi and Paul Chow and Alberto Leon-Garcia}, title = {A Scheduler ASIC for a Programmable Packet Switch}, journal ={IEEE Micro}, volume = {20}, number = {1}, issn = {0272-1732}, year = {2000}, pages = {42-48}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.820052}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - A Scheduler ASIC for a Programmable Packet Switch IS - 1 SN - 0272-1732 SP42 EP48 EPD - 42-48 A1 - L. Louis Zhang, A1 - Brent Beacham, A1 - Massoud Reza Hashemi, A1 - Paul Chow, A1 - Alberto Leon-Garcia, PY - 2000 VL - 20 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.820052
We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch.
Citation:
L. Louis Zhang, Brent Beacham, Massoud Reza Hashemi, Paul Chow, Alberto Leon-Garcia, "A Scheduler ASIC for a Programmable Packet Switch," IEEE Micro, vol. 20, no. 1, pp. 42-48, Jan.-Feb. 2000, doi:10.1109/40.820052
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