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A Scheduler ASIC for a Programmable Packet Switch
January/February 2000 (vol. 20 no. 1)
pp. 42-48
We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch.
Citation:
L. Louis Zhang, Brent Beacham, Massoud Reza Hashemi, Paul Chow, Alberto Leon-Garcia, "A Scheduler ASIC for a Programmable Packet Switch," IEEE Micro, vol. 20, no. 1, pp. 42-48, Jan.-Feb. 2000, doi:10.1109/40.820052
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