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Cache Memory Design for Internet Processors
January/February 2000 (vol. 20 no. 1)
pp. 28-33
We evaluate a series of three progressively more aggressive routing-table cache designs and demonstrate that the incorporation of hardware caches into Internet processors, combined with efficient caching algorithms can significantly improve overall packet forwarding performance.
Citation:
Tzi-cker Chiueh, Prashant Pradhan, "Cache Memory Design for Internet Processors," IEEE Micro, vol. 20, no. 1, pp. 28-33, Jan.-Feb. 2000, doi:10.1109/40.820050
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