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Issue No.04 - July/August (1999 vol.19)
pp: 48-55
ABSTRACT
Designing RISC microprocessor cores for high-performance embedded systems requires a different perspective from system and processor architects. SandCraft, Inc. has developed its latest generation MIPS cores, emphasizing the need for a high degree of leverage between members of the microprocessor family. The Montage architecture introduces some novel features, such as accommodating extensions for added flexibility, which allow the processors to meet customer requirements. Already two family members, the SR1 and SR1-GX, have been implemented using the Montage architecture. These two cores were extensively modeled to verify their capabilities. The SR1 is optimized for high integer and floating-point performance, while the SR1-GX is an SR1 extended with a vector/scalar floating-point capability for accelerating 3D graphics applications.
CITATION
Jack Choquette, Mayank Gupta, Dominic McCarthy, Jack Veenstra, "High-Performance RISC Microprocessors", IEEE Micro, vol.19, no. 4, pp. 48-55, July/August 1999, doi:10.1109/40.782567
REFERENCES
1. VeenstraJ.E. and R.J. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," Proc. Second Int'l Workshop Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, IEEE Computer Society Press, Los Alamitos, Calif., ISBN 0-8186-5292-6, Jan. 1994, p. 201.
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