Issue No.04 - July/August (1999 vol.19)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.782566
This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. Instruction decode and clock skew control achieve real-time MPEG-2 decoding and DVC encoding/decoding for a 2.3 V 300 MHz multimedia processor. The processor contains a CPU core, dedicated hardware, 32 Kbytes of data RAM, and 64 Kbytes of instruction RAM. By using advanced circuit techniques, including dynamic logic for decode together with place-and-route tools, the large instruction RAM meets the timing requirements for the 3.3 ns clock for fetch and decode. The careful design of both global and local clock networks attains a clock skew of 0.238 ns. The chip's 6.7 million transistors are integrated into an area of 8.77x8.28 mm2 in a 0.25-micron CMOS process.
Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba, "The D30V/MPEG Multimedia Processor", IEEE Micro, vol.19, no. 4, pp. 38-47, July/August 1999, doi:10.1109/40.782566