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Micro-RISC Architecture for the Wireless Market
July/August 1999 (vol. 19 no. 4)
pp. 30-37
This article discusses the low-power features of Motorola's M*CORE architecture, the first processor designed specifically for sophisticated, yet low-power, applications. A dual-processor solution for a TDMA baseband transceiver, currently in production, is also described. The key features of the 1.8-volt DSP56652 cellular baseband processor, currently designed into the iDEN i1000 phone, highlights the integration of smart peripherals to reduce overall power consumption.

1. Architectural Brief, "M•CORE microRISC Engine, MCORE 1/D," Motorola Inc., 1999; seewww.mot.com/SPS/MCOREinfo_documentation.htm .
2. J. Scott et al., "Designing the Low-Power M•CORE Architecture," Proc. Int'l Symp. Computer Architecture Power Driven Microarchitecture Workshop, July 1998, pp. 145-150; obtain copies from D.R. Gonzales.
3. K. Harper Motorola M•CORE Technology Center, Austin, Tex.; see www.mot.com/SPS/MCOREinfo_contact.htm .
4. S. King Motorola Wireless Group, Austin, Tex.; seewww.mot.com/SPS/WIRELESScontact.html.
5. Motorola Wireless Group Web site, www.mot.com/SPSWIRELESS, 1999.
6. DSP56652 User's Manual, Motorola Inc., 1999; seewww.mot.com/SPS/WIRELESS/documentationindex.html .

Citation:
David Ruimy Gonzales, "Micro-RISC Architecture for the Wireless Market," IEEE Micro, vol. 19, no. 4, pp. 30-37, July-Aug. 1999, doi:10.1109/40.782565
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