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Performance Analysis and Validation of the picoJava Processor
May/June 1999 (vol. 19 no. 3)
pp. 66-71
picoJava performance modeling and Validation use simulator checkpoints to speed Register Transfer Level (RTL) model simulation. In the process of designing high-performance microprocessors, architects and designers build processor models at varying levels of abstraction for a range of purposes, such as simulating and verifying the processor, predicting processor performance, and developing operating systems and applications for the processor before silicon is available. Such models can range in complexity, from simple analytical performance models in spreadsheet format to the detailed design expressed in a Hardware Description Language (HDL). Other models that fall in between on the range of complexity include instruction-accurate simulators, trace-driven performance simulators, and cycle-accurate simulators. There is usually a trade-off between runtime performance and accuracy while using these models.

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Sudheendra Hangal, Mike O'Connor, "Performance Analysis and Validation of the picoJava Processor," IEEE Micro, vol. 19, no. 3, pp. 66-71, May-June 1999, doi:10.1109/40.768505
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