Issue No.03 - May/June (1999 vol.19)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.768504
In 1995, the IBM[R]1 AS/400[R] changed the architecture of its microprocessors to 64 bit, PowerPC AS[tm]. This entailed not only developing new processors, but also a very large software project. As is typical in such a large software project, the emphasis of the first release was on solid design, good encapsulation, and enhanced functionality with the majority of the performance optimizations being deferred to the subsequent releases. In order to ensure that the system would perform optimally for large and complex OLTP workloads running on the second generation of hardware (which grew the largest SMP from a 4-way to a 12-way), a team of software and hardware experts from several areas was assembled to analyze the system and identify bottlenecks and areas for improvement. This paper will describe the tools and methodology used by this team to perform the analysis and identify the performance improvements. The result of this effort was achieving 25,149 tpmC on the TPC-C benchmark on the new 12-way system. When this system first became available in August 1997, this was the 4th highest tpmC and it had the highest tpmC of any single system (non-cluster) available.
Steven Kunkel, Bill Armstrong, Philip Vitale, "System Optimization for OLTP Workloads", IEEE Micro, vol.19, no. 3, pp. 56-64, May/June 1999, doi:10.1109/40.768504