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Issue No.02 - March/April (1999 vol.19)
pp: 58-69
ABSTRACT
High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL 3D rendering, and X11 and Windows/NT 2D rendering. Since our pin budget limited memory bandwidth, we designed Neon from the memory system upward to reduce bandwidth requirements. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital's Alpha CPUs. Neon-based boards compete well against other workstation accelerators, but cost much less due to a small part count and use of commodity SDRAMs.
INDEX TERMS
3D graphics accelerator, graphics pipeline, rasterization, chunk rendering, tile rendering, texture cache
CITATION
Joel McCormack, Robert McNamara, Christopher Gianos, Norman P. Jouppi, Todd Dutton, John Zurawski, Larry Seiler, Ken Correll, "Implementing Neon: A 256-Bit Graphics Accelerator", IEEE Micro, vol.19, no. 2, pp. 58-69, March/April 1999, doi:10.1109/40.755468
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