Issue No.01 - January/February (1999 vol.19)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.748797
There is a growing demand to validate and test designs that integrate a multitude of discrete, standard and commercial off the shelf (COTS) components and software. Often, the proprietary nature of COTS further complicates the validation process by prohibiting designers from implementing a robust test and validation strategy. In order to preserve a vendor's intellectual property, a customer is often provided a high level model, with limited access to its internals. This limitation may preclude a customer from fully exercising their embedded designs, which may create safety issues for some embedded systems. The increasing use of high level models is creating a need for tools that are capable of testing and validating COTS components in conjunction with an engineer's more detailed design. Unfortunately, simulation tools currently available are incapable of simulating multilevel designs, which include gate, RTL and behavioral levels. Those tools that do attempt to solve these problems resort to merging simulators together, each targeted at handling a specific level of abstraction. This approach incurs high communication overhead between simulators, as well as impaired observation and accuracy.
concurrent fault simulation, multilevel modeling, behavioral modeling, system verification
Karen Panetta Lentz, Jamie Heller, Pier Luca Montessoro, "System Verification Using Multilevel Concurrent Simulation", IEEE Micro, vol.19, no. 1, pp. 60-67, January/February 1999, doi:10.1109/40.748797