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ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure
January/February 1999 (vol. 19 no. 1)
pp. 30-41
ATLAS I is a single-chip ATM switch with 10 Gb/s throughput, a shared buffer, 3 priority levels, multicasting, load monitoring, and optional credit-based flow control. It is a 6-million-transistor chip in 0.35-micron CMOS technology. We present here its implementation; we report on the design complexity and silicon cost of the chip and of the individual functions that it supports. Based on these metrics, we evaluate the architecture of the switch. The evaluation points in the direction of increasing the cell buffer size and dropping VP/VC translation, while other possible modifications are also discussed. The cost of credit support (10% in chip area and 4% in chip power) is minuscule compared to its benefits, i.e. compared to what alternative architectures have to pay in order to achieve comparable performance levels.
Index Terms:
single-chip ATM switch, general-purpose building block for networking, credit-based flow control, backpressure, VLSI switch implementation cost & evaluation.
Citation:
Georgios Kornaros, Dionisios Pnevmatikatos, Panagiota Vatsolaki, Georgios Kalokerinos, Chara Xanthaki, Dimitrios Mavroidis, Dimitrios Serpanos, Manolis Katevenis, "ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure," IEEE Micro, vol. 19, no. 1, pp. 30-41, Jan.-Feb. 1999, doi:10.1109/40.748794
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