Issue No.04 - July/August (1998 vol.18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.710871
The explosive growth of wireless communications, combined with the rapid advances in high-performance portable computing, are driving the microelectronics industry toward the development of a variety of multi-functional, low-cost, yet high-performance, mixed-signal electronic products. The semiconductor industry appears to be confident that, even without any major breakthroughs in photolithography, it will be able to achieve device feature sizes in the order of 100 nm by the year 2006. This reduction in feature size implies significantly higher device switching speeds and faster circuits. More specifically, microprocessors with 3 GHz on-chip clock frequency are within reach by the year 2006. The realization of such high-performance, multi-functional systems calls for novel, often revolutionary, practices in functional-block integration and packaging. In particular, the chip, package and even the board, cannot be designed independently anymore. Instead, a holistic design approach is needed, with interconnect performance and electromagnetic compatibility imposed as primary design constraints. Some of the challenges associated with the electrical design of such systems are discussed in this article.
Modeling and simulation, microelectronics, ICs, microprocessor design, interconnects
Andreas C. Cangellaris, "Electrical Modeling and Simulation Challenges in Chip-Package Codesign", IEEE Micro, vol.18, no. 4, pp. 50-59, July/August 1998, doi:10.1109/40.710871