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Area I/O's Potential for Future Processor Systems
July/August 1998 (vol. 18 no. 4)
pp. 42-49
"The next performance increase in microprocessor systems is waiting just behind the corner". This statement seems to be proven every year when the new generation of microprocessors is launched. Although one cannot deny that progress is made primarily at chip level and that it is much slower on the system level: Whereas state-of-the-art processors already today show internal clock rates being predicted for the future as shown in the NTRS road map (Table 1), the external clock rate and especially memory bus width cannot keep up with this development. Even by adding several levels of cache hierarchies to overcome this discrepancy between off-chip bandwidth and on-chip speed, the maximum latency will enlarge more and more [1]. Today, even the I/O bus proposed in the road map are difficult to connect to the outside world. Thus, performance figures as bandwidth, latency, system speed, and not to forget, size of future microprocessor systems are highly dependent on the interconnection technologies. In fact, when taking into account the expected feature size reduction due to semiconductor technology improvements, interconnection will be the performance show stopper.
Citation:
Etienne Hirt, Michael Scheffler, Jean-Pierre Wyss, "Area I/O's Potential for Future Processor Systems," IEEE Micro, vol. 18, no. 4, pp. 42-49, July-Aug. 1998, doi:10.1109/40.710870
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