Issue No.04 - July/August (1998 vol.18)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.710867
A new three-dimensional (3D) integration technology to achieve system-on-silicon LSIs has been proposed. Several LSI wafers are vertically stacked and glued each other after thinning them in this 3D integration technology. Therefore, this technology can be considered as both 3D LSI technology and a wafer-scale 3D chip-on-chip packaging technology. Effective packing density can be significantly increased by stacking several chips in the vertical direction. In addition, a huge number of interconnections are formed through these stacked chips. Therefore, the chip-package co-design considering the 3D distribution of generated heat and the 3D routing of wirings becomes very important to realize 3D LSIs or 3D multichip modules (3D-MCMs) using this new integration technology. Various kinds of new system-on-silicon LSIs or system LSIs based on this 3D integration technology have been proposed. A real time microvision system has been described as a typical example of the systems realized by using this new 3D integration technology. Several key technologies for this 3D integration such as formation of buried interconnection and microbump, wafer thinning, wafer alignment and wafer bonding have been described.
Large-scale integration, 3D LSI technology, chip packaging, chip-package codesign, multichip modules
Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani, "Future System-on-Silicon LSI Chips", IEEE Micro, vol.18, no. 4, pp. 17-22, July/August 1998, doi:10.1109/40.710867