|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
V830R/AV: Embedded Multimedia Superscalar RISC Processor
March/April 1998 (vol. 18 no. 2)
pp. 36-47
| ASCII Text | x | ||
| Kazumasa Suzuki, Tomohisa Arai, Kouhei Nadehara, Ichiro Kuroda, "V830R/AV: Embedded Multimedia Superscalar RISC Processor," IEEE Micro, vol. 18, no. 2, pp. 36-47, March/April, 1998. | |||
| BibTex | x | ||
| @article{ 10.1109/40.671401, author = {Kazumasa Suzuki and Tomohisa Arai and Kouhei Nadehara and Ichiro Kuroda}, title = {V830R/AV: Embedded Multimedia Superscalar RISC Processor}, journal ={IEEE Micro}, volume = {18}, number = {2}, issn = {0272-1732}, year = {1998}, pages = {36-47}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.671401}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - V830R/AV: Embedded Multimedia Superscalar RISC Processor IS - 2 SN - 0272-1732 SP36 EP47 EPD - 36-47 A1 - Kazumasa Suzuki, A1 - Tomohisa Arai, A1 - Kouhei Nadehara, A1 - Ichiro Kuroda, PY - 1998 KW - multimedia KW - processors KW - signal processing KW - RISC KW - memory architecture VL - 18 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.671401
The construction of real multimedia systems based on processors instead of special purpose hardware requires both higher signal processing performance and higher bandwidth memory systems to the processor. For these applications, a 32-bit embedded RISC processor with a 64-bit "single-instruction multiple-data (SIMD)" coprocessor, the V830R/AV, has been developed. Its asymmetric dual-issue superscalar architecture with the 64-bit SIMD coprocessor achieves 2-GOPS performance in video signal processing applications. The 200-MHz V830R/AV incorporates a Concurrent Rambus DRAM interface that has a 600-Mbyte/s data transfer rate, and it also integrates several multimedia-oriented peripherals. This results in a processor-based real-time MPEG-2 MP@ML decoding system in a unified memory architecture environment.
Index Terms:
multimedia, processors, signal processing, RISC, memory architecture
Citation:
Kazumasa Suzuki, Tomohisa Arai, Kouhei Nadehara, Ichiro Kuroda, "V830R/AV: Embedded Multimedia Superscalar RISC Processor," IEEE Micro, vol. 18, no. 2, pp. 36-47, March-April 1998, doi:10.1109/40.671401
Usage of this product signifies your acceptance of the Terms of Use.