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Implementing Degradable Processing Arrays
January/February 1998 (vol. 18 no. 1)
pp. 64-74
Single-package processing systems are demanded by today's performance-driven network technology and multimedia-enabled applications. The single-packaging of large systems can be realized with wafer scale integration (WSI) technology, however, reliability issues related to large systems continue to plague WSI. Fault tolerance by way of reconfiguration has not found widespread use in WSI due to the extra real estate required for reconfiguration hardware. Multichip modules (MCMs) with their various implementation options provide an ideal technology for fault-tolerant processor arrays. A commercially-feasible MCM-based fault tolerance scheme that incurs no increase to primary circuit area is presented. The scheme facilitates the continued operation of a defective array that would otherwise be discarded. With minimal additional hardware and scheduling overhead, a healthy subarray is extracted from the original array such that original array topology is preserved. Details of the reconfiguration algorithm, switch control, and switch implementation are presented.
Index Terms:
Fault-tolerance, multichip modules, processing arrays, reconfiguration
Citation:
Stephanie R. Goldberg, Shambhu J. Upadhyaya, "Implementing Degradable Processing Arrays," IEEE Micro, vol. 18, no. 1, pp. 64-74, Jan.-Feb. 1998, doi:10.1109/40.653036
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