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A Tracking Clock Recovery Receiver for 4-Gbps Signaling
January/February 1998 (vol. 18 no. 1)
pp. 25-27
| ASCII Text | x | ||
| John Poulton, William J. Dally, Steve Tell, "A Tracking Clock Recovery Receiver for 4-Gbps Signaling," IEEE Micro, vol. 18, no. 1, pp. 25-27, January/February, 1998. | |||
| BibTex | x | ||
| @article{ 10.1109/40.653023, author = {John Poulton and William J. Dally and Steve Tell}, title = {A Tracking Clock Recovery Receiver for 4-Gbps Signaling}, journal ={IEEE Micro}, volume = {18}, number = {1}, issn = {0272-1732}, year = {1998}, pages = {25-27}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.653023}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - A Tracking Clock Recovery Receiver for 4-Gbps Signaling IS - 1 SN - 0272-1732 SP25 EP27 EPD - 25-27 A1 - John Poulton, A1 - William J. Dally, A1 - Steve Tell, PY - 1998 KW - High-speed signaling KW - clock recovery KW - equalization KW - interconnections VL - 18 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.653023
Results of an experimental 0.5-micron CMOS, 4-Gbps signaling chip show the effectiveness of a simple transition-filter equalization technique. The chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data "eye."
Index Terms:
High-speed signaling, clock recovery, equalization, interconnections
Citation:
John Poulton, William J. Dally, Steve Tell, "A Tracking Clock Recovery Receiver for 4-Gbps Signaling," IEEE Micro, vol. 18, no. 1, pp. 25-27, Jan.-Feb. 1998, doi:10.1109/40.653023
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