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Virtual-Address Caches, Part 2: Multiprocessor Issues
November/December 1997 (vol. 17 no. 6)
pp. 69-74
In order to support virtual memory, virtual addresses must be efficiently translated into physical addresses. Traditionally, this dynamic translation has been done in a Translation Lookaside Buffer (TLB) before or in parallel with the cache access, so that the cache is indexed and tagged with physical addresses. Consistency problems add complexity to virtual-address caches. The main sources of these problems are the presence of synonyms and address-mapping changes. In this first part of this two-part survey, we introduced the problems and discussed solutions in the context of single-processor systems. In Part 2 of, we address multiprocessor issues. In multiprocessors, coherence of caches and TLBs must be maintained. The virtual caches can take advantage of these mechanisms. Therefore, some solutions make more sense than others in a multiprocessor environment.
Index Terms:
Caches, microprocessors, uniprocessor architecture, multiprocessor architecture
Michel Cekleov, Michel Dubois, "Virtual-Address Caches, Part 2: Multiprocessor Issues," IEEE Micro, vol. 17, no. 6, pp. 69-74, Nov.-Dec. 1997, doi:10.1109/40.641599
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