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Superscalar Instruction Issue
September/October 1997 (vol. 17 no. 5)
pp. 28-39
While providing a considerable potential for parallel execution, the performance of a superscalar microarchitecture depends heavily on the particular instruction issue scheme chosen. In this paper, we focus on the instruction issue task of superscalar processors. We first identify the design space of superscalar instruction issue by indicating important design aspects and associated design choices. Through the use of DS-trees we represent the design space in a concise graphical way. We also explore it by showing the design choices made in recent superscalar processors, highlighting the most frequently used issue schemes and prevailing trends.
Index Terms:
Instruction issue, instruction dispatch, design space, microarchitecture, superscalar processors
Citation:
Dezsõ Sima, "Superscalar Instruction Issue," IEEE Micro, vol. 17, no. 5, pp. 28-39, Sept.-Oct. 1997, doi:10.1109/40.621211
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