Issue No.02 - March/April (1997 vol.17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.592310
The PA-8000 RISC CPU is the first implementation of a new generation of microprocessors from Hewlett-Packard Company. The processor was designed for high-end systems and to support the new 64-bit PA-RISC 2.0 architecture. The aggressive four-way superscalar implementation also features speculative, out-of-order execution combined with ten independent functional units, allowing it to attain true leadership performance. Large single-level caches are provided off-chip. At the heart of the out-of-order execution capability of the machine is a high performance, 56-entry Instruction Reorder Buffer. The complexities of tracking many types of dependencies in this large instruction window and determining which instructions to issue for execution will be included. The chip is fabricated in a 0.5 micron, 3.3V CMOS process, resulting in a 17.68x19.1 mm die with 3.8 million transistors. A robust 64-bit, 768 MB/s split-transaction system bus supplies the CPU with instructions and data, and provides for multiprocessing.
Hewlett-Packard, PA-8000, microprocessor, out-of-order, superscalar, speculative execution.
Ashok Kumar, "The HP PA-8000 RISC CPU", IEEE Micro, vol.17, no. 2, pp. 27-32, March/April 1997, doi:10.1109/40.592310