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A Time-Multiplexed Reconfigurable Neuroprocessor
January/February 1997 (vol. 17 no. 1)
pp. 58-65
We present the architecture and VLSI circuit design of a multilayered pulse-stream neuroprocessor. This neuroprocessor design uses a mixed analog/digital implementation to obtain an efficient use of chip area and operating speed. The processing element (PE) weights are stored digitally in local dynamic cyclic shift registers. These 7-bit signed weights allow both excitatory as well as inhibitory connection strengths to be incorporated. The weights are trained externally and downloaded onto the network. The computational units are analog and consist of a multiplying charge-scaling digital-to-analog converter and a neural activity integrator. They operate at a clock frequency of 10 MHz, delivering a performance of 2.5-billion connections per second for a typical 64-element, 4-layered network, based on a 1-micron CMOS technology process.
Index Terms:
Neuroprocessing, reconfigurable architecture, VLSI design, mixed analog/digital design
Fadi N. Sibai, Sunil D. Kulkarni, "A Time-Multiplexed Reconfigurable Neuroprocessor," IEEE Micro, vol. 17, no. 1, pp. 58-65, Jan.-Feb. 1997, doi:10.1109/40.566208
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