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Tiny Tera: A Packet Switch Core
January/February 1997 (vol. 17 no. 1)
pp. 26-33
Tiny Tera is a small packet switch with an aggregate bandwidth of approximately 1 terabit per second. The CMOS-based, input-queued, fixed-size packet switch suits a wide range of applications such as a high-performance ATM switch, the core of an Internet router, or as a fast multiprocessor interconnect. Using off-the-shelf technology, we plan to demonstrate that a very high bandwidth switch can be built without the need for esoteric optical switching technology. By employing novel scheduling algorithms for both unicast and multicast traffic, the switch will have a maximum throughput close to 100%. Using novel high-speed, chip-to-chip serial link technology, we plan to reduce the physical size and complexity of the switch, as well as the system pin count.
Index Terms:
Packing switching, Internet routing, interconnects, optical switching, multicast transmission
Citation:
Nick McKeown, Martin Izzard, Adisak Mekkittikul, William Ellersick, Mark Horowitz, "Tiny Tera: A Packet Switch Core," IEEE Micro, vol. 17, no. 1, pp. 26-33, Jan.-Feb. 1997, doi:10.1109/40.566194
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