Issue No.05 - October (1996 vol.16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.540082
A major distinguishing feature of RISC processor architectures is the organization of their register files. They basically fall into three categories: a flat register file as in MIPS processors, fixed--size register windows as in the SPARC processor line, and a stack-like organization as in the AM29K processors. The purpose of this paper is to introduce a RISC processor architecture Fast with a unique stack system. It has been designed with the special needs of functional languages in mind. To demonstrate the suitability of this architecture for conventional languages, we have implemented a C compiler for it. This paper gives an overview over the important parts of the architecture. It describes the adaptation of a standard C compiler to this architecture, and compares the resulting performance with SPARC and MIPS implementations.
RISC processor architecture, register file organization, stack, C compilation, benchmarks.
Claus Assmann, "Compiling C on a Multiple-Stack Architecture", IEEE Micro, vol.16, no. 5, pp. 60-67, October 1996, doi:10.1109/40.540082