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| Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato, "Two-Chip MPEG-2 Video Encoder," IEEE Micro, vol. 16, no. 2, pp. 51-58, April, 1996. | |||
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| @article{ 10.1109/40.491462, author = {Toshio Kondo and Kazuhito Suguri and Mitsuo Ikeda and Tetsuya Abe and Hiroaki Matsuda and Tsuneo Okubo and Kenji Ogura and Yutaka Tashiro and Naoki Ono and Toshihiro Minami and Ritsu Kusaba and Takeshi Ikenaga and Nobutaro Shibata and Ryota Kasai and Koji Otsu and Fumiaki Nakagawa and Yasuhiko Sato}, title = {Two-Chip MPEG-2 Video Encoder}, journal ={IEEE Micro}, volume = {16}, number = {2}, issn = {0272-1732}, year = {1996}, pages = {51-58}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.491462}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Two-Chip MPEG-2 Video Encoder IS - 2 SN - 0272-1732 SP51 EP58 EPD - 51-58 A1 - Toshio Kondo, A1 - Kazuhito Suguri, A1 - Mitsuo Ikeda, A1 - Tetsuya Abe, A1 - Hiroaki Matsuda, A1 - Tsuneo Okubo, A1 - Kenji Ogura, A1 - Yutaka Tashiro, A1 - Naoki Ono, A1 - Toshihiro Minami, A1 - Ritsu Kusaba, A1 - Takeshi Ikenaga, A1 - Nobutaro Shibata, A1 - Ryota Kasai, A1 - Koji Otsu, A1 - Fumiaki Nakagawa, A1 - Yasuhiko Sato, PY - 1996 KW - MPEG KW - motion compensation/coding/control KW - video compression KW - PC video boards VL - 16 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/40.491462
We have developed a real-time MPEG2 (simple profile at main level) encoder chip set with ENC-M for motion compensation and ENC-C for coding/control. This set has full functions and sufficient processing power for real-time compression of NTSC 4:2:0 video signals (720 x 480 pels, 30 frames/s), with only three external memories: 4-Mbit VRAM, 16-Mbit synchronous DRAM, and 2-Mbit FIFO-structured DRAM. These features enable us to implement, for example, a small PC board for NTSC video CODEC.
Index Terms:
MPEG, motion compensation/coding/control, video compression, PC video boards
Citation:
Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato, "Two-Chip MPEG-2 Video Encoder," IEEE Micro, vol. 16, no. 2, pp. 51-58, April 1996, doi:10.1109/40.491462
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