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Developing the AMD-K5 Architecture
April 1996 (vol. 16 no. 2)
pp. 16-26
ASCII Text
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Dave Christie, "Developing the AMD-K5 Architecture," IEEE Micro, vol. 16, no. 2, pp. 16-26, April, 1996.
 
 
BibTex
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@article{ 10.1109/40.491459,
author = {Dave Christie},
title = {Developing the AMD-K5 Architecture},
journal ={IEEE Micro},
volume = {16},
number = {2},
issn = {0272-1732},
year = {1996},
pages = {16-26},
doi = {http://doi.ieeecomputersociety.org/10.1109/40.491459},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Developing the AMD-K5 Architecture
IS - 2
SN - 0272-1732
SP16
EP26
EPD - 16-26
A1 - Dave Christie,
PY - 1996
KW - microprocessor
KW - X86 architecture
KW - superscalar
KW - speculative execution
KW - out-of-order execution
VL - 16
JA - IEEE Micro
ER -
 
The K5TM microprocessor project at AMD created the basis for Advanced Micro Devices' first independently designed implementations of the x86 architecture. The first-time nature of this project, coupled with the complexity of the x86 architecture, presented many unique challenges and constraints to the designers. Nevertheless, the end result is the only x86-compatible microprocessor architecture that can speculatively decode and execute up to four x86 instructions at a time, with out-of-order instruction execution. An equally significant result of the project is a very robust x86 development and verification methodology.
Index Terms:
microprocessor, X86 architecture, superscalar, speculative execution, out-of-order execution
Citation:
Dave Christie, "Developing the AMD-K5 Architecture," IEEE Micro, vol. 16, no. 2, pp. 16-26, April 1996, doi:10.1109/40.491459
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