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Precise Interrupts
February 1996 (vol. 16 no. 1)
pp. 58-67
Interrupts and in particular precise interrupts constitute an integral part of all computer architectures. Implementing precise interrupts can substantially inhibit the performance of computers. To gain some insight into the problem, we divide common interrupts into four classes, and examine the cost of implementing precise interrupts. Two of these classes, external-critical and external-error, can be implemented cheaply on a pipelined processor, with little or no impact on performance. We propose that interrupts be implemented imprecisely, except during debugging, of a third class of interrupts, internal-error interrupts. Finally, we introduced some techniques that can be used to cheaply implement precise interrupts for the fourth class of interrupts, internal-critical interrupts, but may not apply generally. While the central concern is precision, or lack thereof, we also deal with several peripheral issues that arise when implementing interrupts on aggressive implementations. These include sparse restart, which will arise whenever we weaken the requirements for precision on an out-of-order issue processor, and the impact of parallel (e.g., superscalar) issue.
Index Terms:
precise interrupts, exceptions, traps, interrupt handlers, pipelining, out-of-order issue processors, superscalar processors, instruction level parallel processors.
Citation:
Mayan Moudgill, Stamatis Vassiliadis, "Precise Interrupts," IEEE Micro, vol. 16, no. 1, pp. 58-67, Feb. 1996, doi:10.1109/40.482313
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