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SH3: High Code Density, Low Power
December 1995 (vol. 15 no. 6)
pp. 11-19
Hitachi's SH series represents a 32-bit RISC architecture with 16-bit fixed-length instruction set. SH3 is a pipelined implementation of the SH architecture with on-chip cache, MMU, and software programmable power management. This article briefly describes the SH architecture and SH3 implementation, and establishes the advantages of such an instruction set. SH3 achieves 60-Dhrystone MIPS of performance and dissipates 400 mW at 60 MHz. Higher code density and corresponding improvement in instruction fetch latency leads to higher performance as compared with typical 32-bit RISC architectures. Small die size, low power consumption, and software-controlled power management capability make SH3 an ideal microprocessor for embedded applications such as nomadic computing systems or multimedia systems.
Index Terms:
Hitachi SH series, microprocessors, RISC, low power computing, code density
Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas, "SH3: High Code Density, Low Power," IEEE Micro, vol. 15, no. 6, pp. 11-19, Dec. 1995, doi:10.1109/40.476254
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