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A Multilevel Systolic Approach for Fuzzy Inference Hardware
October 1995 (vol. 15 no. 5)
pp. 61-71
We describe a digital architecture to evaluate fuzzy inferences. This architecture is based on a novel systolic structure in the field of fuzzy processing that is called multilevel systolic approach. Its main features are: high throughput, perfomance independent of the fuzzy model size supported, high flexibility to resize the parameters of the design, max-min inference, and capability for a considerable amount of complex rules without loss of efficiency. The circuit development has been carried out by using a VHDL simulator, with ES2 1um standard cells, and its results has given a perfomace over 10 mega fuzzy logic rule base inferences per second.
Index Terms:
fuzzy, fuzzy hardware, fuzzy inference, systolics
Citation:
Luis de Salvador, Julio Gutiérrez, "A Multilevel Systolic Approach for Fuzzy Inference Hardware," IEEE Micro, vol. 15, no. 5, pp. 61-71, Oct. 1995, doi:10.1109/40.464591
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