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Processor Implementations Using Queues
August 1995 (vol. 15 no. 4)
pp. 58-66
This survey paper examines two processor-memory interface problems - long latency and low bandwidth, and the use of queues to resolve them. Queues are classified by data type and prefetch strategies. Queue characteristics and parameters are also discussed. The use of queues to support variable length instructions and reduce misalignment problems are presented. Several example architectures are given in historical perspective - from the IBM 7030 (Stretch) to the Motorola/Apple/IBM PowerPC 601. Each application is detailed, giving queue configurations and prefetch strategies along with the design decisions that lead to their final architectures.
Index Terms:
Queues, Instruction Queues, Branch Target Queues, Data Queues, Prefetch Strategies, Buffers, Latency, Bandwidth, Instruction Alignment
Michael K. Milligan, Harvey G. Cragon, "Processor Implementations Using Queues," IEEE Micro, vol. 15, no. 4, pp. 58-66, Aug. 1995, doi:10.1109/40.400642
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