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A Low-Power Network for On-Line Diagnosis of Heart Patients
June 1995 (vol. 15 no. 3)
pp. 18-25
A system has been developed for the classification of Intracardiac Electrograms (ICEG). The system is comprised of an analog VLSI neural network, an Implantable Cardioverter Defibrillator (ICD) and a PC-based software training environment. Analog implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network architecture reduces the impact of noise, drift, and offsets inherent in analog approaches. The neural network chip is a 10:6:3 multilayer perceptron with on- chip digital weight storage, a bucket brigade input to feed the ICEG to the network and a winner-take-all circuit at the output. The chip was implemented in 1.2-um CMOS and consumes less than 200-nW maximum average power in an area of 2.2x2.2mm2. The network was trained in loop with the ICD in the signal processing path. Results are presented, demonstrating the advantages of combining neural network and and low-power analog circuit techniques by distinguishing certain dangerous arrhythmia, not currently possible in existing ICDs.
Index Terms:
Neural networks, low-power design, analog circuits, medical systems
Citation:
Richard Coggins, Marwan Jabri, Barry Flower, Stephen Pickard, "A Low-Power Network for On-Line Diagnosis of Heart Patients," IEEE Micro, vol. 15, no. 3, pp. 18-25, June 1995, doi:10.1109/40.387678
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